1. Field of the Invention
The present invention is generally directed to the field of integrated circuits, and, more particularly, to an integrated circuit having an output buffer with slew rate control and a selection circuit for producing a desired slew rate in the output buffer.
2. Description of the Related Art
Integrated circuit devices have become quite commonplace in the modern world. A modern computer system may include hundreds, if not thousands, of integrated circuit devices. Over the years, the individual integrated circuit devices themselves have become extremely complex, and their interaction with one another, for example in a modern computer system, has also become much more complex. The timing of various signals between integrated circuit devices in a computer system, for example, is now much more critical than in early computer systems. Standards have been promulgated to govern the timing of signals between integrated circuit devices. Various bus architectures used in personal computers, for example, have specifications controlling the timing of various signals as well as the speed with which various signals must become “valid.” As an example, some bus specifications require that a signal become “valid” within a specified period of time following a triggering event.
To meet such timing requirements, many integrated circuits that provide output signals employ some form of “slew rate” control. “Slew rate” is the rate at which an output voltage, for example, transitions from a “low” value to a “high” value, or from a “high” value to a “low” value. Some devices have attempted to control the slew rate by restricting the range of process variables, voltage and temperature. Other devices attempt to control the slew rate by turning on the output signal in stages. That is, an output signal from a particular integrated circuit device may be driven by two or more output stages, and the two or more stages will be turned on in sequence to control the slew rate. Many Universal Serial Bus drivers use a capacitive feedback from the output to the predriver stage. These devices attempt to use the gain of the output stage to make the capacitance at the predriver node appear to be very large. In essence, this technique attempts to desensitize the output driver to variations in the output capacitance, allowing greater variation of the output capacitance without undue effect on the slew rate.
However, variation in the output capacitance is not the only factor that affects the slew rate. Variations in manufacturing process parameters, voltage levels in the integrated circuit device and temperature at which the device is operating all contribute to variations in the slew rate at the output stage. In particular, in light of the many factors affecting slew rate, as the load capacitance and process being driven by the output circuit varies through a permitted range, the slew rate of the output signal may fall outside the range required by an applicable specification.
The present invention is directed to solving, or at least reducing, some or all of the aforementioned problems.